#include <stdio.h>
#include "hb_ddr_oem.h"
#include "x3_info.h"

extern struct ddr_dfs_freqs lpddr4_samsung_1g[];
extern unsigned int lpddr4_samsung_1g_cnt;
extern struct ddr_dfs_freqs lpddr4_samsung_2g[];
extern unsigned int lpddr4_samsung_2g_cnt;
extern struct ddr_dfs_freqs lpddr4_3200_333[];
extern unsigned int lpddr4_3200_333_cnt;
/* DRAM PHY init engine image */
struct DRAM_CFG_PARAM ddr4_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s0, 0x10},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s1, 0x400},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s2, 0x10e},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s1, 0x480},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s1, 0x478},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s0, 0x2},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s0, 0x44},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s0, 0x14f},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s1, 0x630},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s0, 0x47},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s0, 0x4f},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s2, 0x179},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s1, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s1, 0x45a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s2, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s0, 0x40},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s2, 0x179},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s1, 0x618},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s0, 0x40c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s0, 0x4040},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s0, 0x40},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s2, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s2, 0x78},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s0, 0x549},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s0, 0xd49},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s0, 0x94a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s0, 0x441},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s0, 0x42},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s0, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s0, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s2, 0x58},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s0, 0x5},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s1, 0x8140},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s1, 0x8138},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s2, 0x101},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s0, 0xf},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s0, 0x47},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s1, 0x630},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s1, 0x618},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s1, 0x8140},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s1, 0x478},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s1, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s2, 0x101},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s2, 0x8},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s2, 0x0},
	{DWC_DDRPHYA_APBONLY0__SequencerOverride, 0x400},
	{DWC_DDRPHYA_INITENG0__StartVector0b0, 0x0},
	{DWC_DDRPHYA_INITENG0__StartVector0b15, 0x2b},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x64},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xc8},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x7d0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p0, 0x2c},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag0, 0x0},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag1, 0x173},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag2, 0x60},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag3, 0x6110},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag4, 0x2152},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag5, 0xdfbd},
#ifdef CONFIG_SUPPORT_PALLADIUM
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag6, 0xffff},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag7, 0x6152},
#else
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag6, 0x2060},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag7, 0x6152},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p0, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p0, 0x3},
#endif
	{DWC_DDRPHYA_MASTER0__CalZap, 0x1},
	{DWC_DDRPHYA_MASTER0__CalRate, 0x19},
	{DWC_DDRPHYA_DRTUB0__UcclkHclkEnables, 0x0},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_ddr4_phy_pie(void)
{
	return ARRAY_SIZE(ddr4_phy_pie);
}

/* DRAM PHY init engine image */
struct DRAM_CFG_PARAM ddr4_2666_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x53},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xa6},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x682},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_ddr4_2666_phy_pie(void)
{
	return ARRAY_SIZE(ddr4_2666_phy_pie);
}

/* DRAM PHY init engine image */
struct DRAM_CFG_PARAM ddr4_2400_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x4b},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0x96},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x5dc},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_ddr4_2400_phy_pie(void)
{
	return ARRAY_SIZE(ddr4_2400_phy_pie);
}

struct DRAM_CFG_PARAM ddr4_1600_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x32},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0x64},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x3e8},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_ddr4_1600_phy_pie(void)
{
	return ARRAY_SIZE(ddr4_1600_phy_pie);
}

struct DRAM_CFG_PARAM ddr4_2640_phy_pie[] = {
        {DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
        {DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x52},
        {DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xa5},
        {DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x672},
        {DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_ddr4_2640_phy_pie(void)
{
        return ARRAY_SIZE(ddr4_2640_phy_pie);
}


/* DRAM PHY init engine image */
struct DRAM_CFG_PARAM lpddr4_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s0, 0x10},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s1, 0x400},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b0s2, 0x10e},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PreSequenceReg0b1s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s1, 0x480},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b0s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b1s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s1, 0x478},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b2s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s1, 0xe8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b3s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s0, 0x2},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b4s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b5s2, 0x139},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s0, 0x44},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b6s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s0, 0x14f},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s1, 0x630},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b7s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s0, 0x47},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b8s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s0, 0x4f},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b9s2, 0x179},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b10s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b11s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s1, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b12s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s1, 0x45a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b13s2, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b14s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s0, 0x40},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b15s2, 0x179},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s1, 0x618},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b16s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s0, 0x40c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b17s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b18s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s0, 0x4040},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b19s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b20s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s0, 0x40},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b21s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b22s2, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b23s2, 0x78},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s0, 0x549},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b24s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s0, 0xd49},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b25s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s0, 0x94a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b26s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s0, 0x441},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b27s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s0, 0x42},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b28s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s1, 0x633},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b29s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b30s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b31s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s0, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b32s2, 0x149},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s0, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b33s2, 0x159},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b34s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s1, 0x3c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b35s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b36s2, 0x48},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b37s2, 0x58},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s0, 0xb},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b38s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b39s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s0, 0x5},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b40s2, 0x109},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x0, 0x811},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x0, 0x880},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x0, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x0, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x1, 0x4008},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x1, 0x83},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x1, 0x4f},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x1, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x2, 0x4040},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x2, 0x83},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x2, 0x51},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x2, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x3, 0x811},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x3, 0x880},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x3, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x3, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x4, 0x720},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x4, 0xf},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x4, 0x1740},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x4, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x5, 0x16},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x5, 0x83},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x5, 0x4b},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x5, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x6, 0x716},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x6, 0xf},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x6, 0x2001},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x6, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x7, 0x716},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x7, 0xf},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x7, 0x2800},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x7, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x8, 0x716},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x8, 0xf},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x8, 0xf00},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x8, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x9, 0x720},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x9, 0xf},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x9, 0x1400},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x9, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x10, 0xe08},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x10, 0xc15},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x10, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x10, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x11, 0x625},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x11, 0x15},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x11, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x11, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x12, 0x4028},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x12, 0x80},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x12, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x12, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x13, 0xe08},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x13, 0xc1a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x13, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x13, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x14, 0x625},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x14, 0x1a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x14, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x14, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x15, 0x4040},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x15, 0x80},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x15, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x15, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x16, 0x2604},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x16, 0x15},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x16, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x16, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x17, 0x708},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x17, 0x5},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x17, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x17, 0x2002},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x18, 0x8},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x18, 0x80},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x18, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x18, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x19, 0x2604},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x19, 0x1a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x19, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x19, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x20, 0x708},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x20, 0xa},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x20, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x20, 0x2002},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x21, 0x4040},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x21, 0x80},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x21, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x21, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x22, 0x60a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x22, 0x15},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x22, 0x1200},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x22, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x23, 0x61a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x23, 0x15},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x23, 0x1300},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x23, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x24, 0x60a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x24, 0x1a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x24, 0x1200},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x24, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x25, 0x642},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x25, 0x1a},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x25, 0x1300},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x25, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq0x26, 0x4808},
	{DWC_DDRPHYA_ACSM0__AcsmSeq1x26, 0x880},
	{DWC_DDRPHYA_ACSM0__AcsmSeq2x26, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmSeq3x26, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b41s2, 0x11a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s1, 0x7aa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b42s2, 0x2a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s1, 0x7b2},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b43s2, 0x2a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b44s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s1, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b45s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s1, 0x2a8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b46s2, 0x129},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s1, 0x370},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b47s2, 0x129},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s1, 0x3c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b48s2, 0x1a9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s0, 0xc},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b49s2, 0x199},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s0, 0x14},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b50s2, 0x11a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b51s2, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s0, 0xe},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b52s2, 0x199},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s1, 0x8568},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b53s2, 0x108},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b54s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b54s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b54s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b55s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b55s1, 0x1d8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b55s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b56s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b56s1, 0x8558},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b56s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b57s0, 0x70},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b57s1, 0x788},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b57s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b58s0, 0x1ff8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b58s1, 0x85a8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b58s2, 0x1e8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b59s0, 0x50},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b59s1, 0x798},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b59s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b60s0, 0x60},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b60s1, 0x7a0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b60s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b61s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b61s1, 0x8310},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b61s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b62s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b62s1, 0xa310},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b62s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b63s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b63s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b63s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b64s0, 0x6e},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b64s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b64s2, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b65s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b65s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b65s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b66s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b66s1, 0x8310},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b66s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b67s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b67s1, 0xa310},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b67s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b68s0, 0x1ff8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b68s1, 0x85a8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b68s2, 0x1e8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b69s0, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b69s1, 0x798},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b69s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b70s0, 0x78},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b70s1, 0x7a0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b70s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b71s0, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b71s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b71s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b72s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b72s1, 0x8b10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b72s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b73s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b73s1, 0xab10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b73s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b74s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b74s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b74s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b75s0, 0x58},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b75s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b75s2, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b76s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b76s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b76s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b77s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b77s1, 0x8b10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b77s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b78s0, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b78s1, 0xab10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b78s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b79s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b79s1, 0x1d8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b79s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b80s0, 0x80},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b80s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b80s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b81s0, 0x18},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b81s1, 0x7aa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b81s2, 0x6a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b82s0, 0xa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b82s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b82s2, 0x1e9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b83s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b83s1, 0x8080},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b83s2, 0x108},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b84s0, 0xf},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b84s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b84s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b85s0, 0xc},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b85s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b85s2, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b86s0, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b86s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b86s2, 0x1a9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b87s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b87s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b87s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b88s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b88s1, 0x8080},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b88s2, 0x108},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b89s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b89s1, 0x7aa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b89s2, 0x6a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b90s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b90s1, 0x8568},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b90s2, 0x108},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b91s0, 0xb7},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b91s1, 0x790},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b91s2, 0x16a},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b92s0, 0x1f},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b92s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b92s2, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b93s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b93s1, 0x8558},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b93s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b94s0, 0xf},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b94s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b94s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b95s0, 0xd},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b95s1, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b95s2, 0x68},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b96s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b96s1, 0x408},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b96s2, 0x169},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b97s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b97s1, 0x8558},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b97s2, 0x168},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b98s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b98s1, 0x3c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b98s2, 0x1a9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b99s0, 0x3},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b99s1, 0x370},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b99s2, 0x129},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b100s0, 0x20},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b100s1, 0x2aa},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b100s2, 0x9},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b101s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b101s1, 0x400},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b101s2, 0x10e},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b102s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b102s1, 0xe8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b102s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b103s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b103s1, 0x8140},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b103s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b104s0, 0x10},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b104s1, 0x8138},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b104s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b105s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b105s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b105s2, 0x101},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b106s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b106s1, 0x448},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b106s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b107s0, 0xf},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b107s1, 0x7c0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b107s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b108s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b108s1, 0xe8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b108s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b109s0, 0x47},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b109s1, 0x630},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b109s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b110s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b110s1, 0x618},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b110s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b111s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b111s1, 0xe0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b111s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b112s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b112s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b112s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b113s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b113s1, 0x8140},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b113s2, 0x10c},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b114s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b114s1, 0x478},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b114s2, 0x109},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b115s0, 0x0},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b115s1, 0x1},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b115s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b116s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b116s1, 0x4},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b116s2, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b117s0, 0x8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b117s1, 0x7c8},
	{DWC_DDRPHYA_INITENG0__SequenceReg0b117s2, 0x101},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b0s2, 0x8},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s0, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s1, 0x0},
	{DWC_DDRPHYA_INITENG0__PostSequenceReg0b1s2, 0x0},
	{DWC_DDRPHYA_APBONLY0__SequencerOverride, 0x400},
	{DWC_DDRPHYA_INITENG0__StartVector0b0, 0x0},
	{DWC_DDRPHYA_INITENG0__StartVector0b8, 0x29},
	{DWC_DDRPHYA_INITENG0__StartVector0b15, 0x6a},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl0, 0x0},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl1, 0x101},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl2, 0x105},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl3, 0x107},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl4, 0x10f},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl5, 0x202},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl6, 0x20a},
	{DWC_DDRPHYA_ACSM0__AcsmCsMapCtrl7, 0x20b},
	{DWC_DDRPHYA_MASTER0__DbyteDllModeCntrl, 0x2},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x85},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0x10a},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0xa6a},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p0, 0x2c},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag0, 0x0},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag1, 0x173},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag2, 0x60},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag3, 0x6110},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag4, 0x2152},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag5, 0xdfbd},
#ifdef CONFIG_SUPPORT_PALLADIUM
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag6, 0xffff},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag7, 0x6152},
#else
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag6, 0x2060},
	{DWC_DDRPHYA_INITENG0__Seq0BDisableFlag7, 0x6152},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p0, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p0, 0x3},
#endif
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p0, 0xe0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p0, 0x12},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p0, 0xe0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p0, 0x12},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p0, 0xe0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p0, 0x12},
	{DWC_DDRPHYA_ACSM0__AcsmCtrl13, 0xf},
	{DWC_DDRPHYA_DBYTE0__TsmByte1, 0x1},
	{DWC_DDRPHYA_DBYTE0__TsmByte2, 0x1},
	{DWC_DDRPHYA_DBYTE0__TsmByte3, 0x180},
	{DWC_DDRPHYA_DBYTE0__TsmByte5, 0x1},
	{DWC_DDRPHYA_DBYTE0__TrainingParam, 0x6209},
	{DWC_DDRPHYA_DBYTE0__Tsm0_i0, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i1, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i2, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i3, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i4, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i5, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i6, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i7, 0x1},
	{DWC_DDRPHYA_DBYTE0__Tsm2_i8, 0x1},
	{DWC_DDRPHYA_DBYTE1__TsmByte1, 0x1},
	{DWC_DDRPHYA_DBYTE1__TsmByte2, 0x1},
	{DWC_DDRPHYA_DBYTE1__TsmByte3, 0x180},
	{DWC_DDRPHYA_DBYTE1__TsmByte5, 0x1},
	{DWC_DDRPHYA_DBYTE1__TrainingParam, 0x6209},
	{DWC_DDRPHYA_DBYTE1__Tsm0_i0, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i1, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i2, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i3, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i4, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i5, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i6, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i7, 0x1},
	{DWC_DDRPHYA_DBYTE1__Tsm2_i8, 0x1},
	{DWC_DDRPHYA_DBYTE2__TsmByte1, 0x1},
	{DWC_DDRPHYA_DBYTE2__TsmByte2, 0x1},
	{DWC_DDRPHYA_DBYTE2__TsmByte3, 0x180},
	{DWC_DDRPHYA_DBYTE2__TsmByte5, 0x1},
	{DWC_DDRPHYA_DBYTE2__TrainingParam, 0x6209},
	{DWC_DDRPHYA_DBYTE2__Tsm0_i0, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i1, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i2, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i3, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i4, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i5, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i6, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i7, 0x1},
	{DWC_DDRPHYA_DBYTE2__Tsm2_i8, 0x1},
	{DWC_DDRPHYA_DBYTE3__TsmByte1, 0x1},
	{DWC_DDRPHYA_DBYTE3__TsmByte2, 0x1},
	{DWC_DDRPHYA_DBYTE3__TsmByte3, 0x180},
	{DWC_DDRPHYA_DBYTE3__TsmByte5, 0x1},
	{DWC_DDRPHYA_DBYTE3__TrainingParam, 0x6209},
	{DWC_DDRPHYA_DBYTE3__Tsm0_i0, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i1, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i2, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i3, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i4, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i5, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i6, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i7, 0x1},
	{DWC_DDRPHYA_DBYTE3__Tsm2_i8, 0x1},
	{DWC_DDRPHYA_MASTER0__CalZap, 0x1},
	{DWC_DDRPHYA_MASTER0__CalRate, 0x19},
	{DWC_DDRPHYA_DRTUB0__UcclkHclkEnables, 0x2},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_phy_pie);
}

/* DRAM PHY init engine image */
struct DRAM_CFG_PARAM lpddr4_100_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x3},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0x6},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x3e},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p0, 0x10},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_100_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_100_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_667_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x14},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0x29},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x1a0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p0, 0x10},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_667_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_667_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_2666_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x2ED},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xa6},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x682},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_2666_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_2666_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_3200_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x64},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xc8},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x7d0},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_3200_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_3200_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_3200_phy_pie_dfs[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x384}, // DFS Workaround 0.5us -> 4.5us
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xc8},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x7d0},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_3200_phy_pie_dfs(void)
{
	return ARRAY_SIZE(lpddr4_3200_phy_pie_dfs);
}

struct DRAM_CFG_PARAM lpddr4_3600_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x70},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xe1},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x8ca},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_3600_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_3600_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_3733_phy_pie[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p0, 0x74},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p0, 0xe9},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p0, 0x91c},
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

uint32_t get_sizeof_lpddr4_3733_phy_pie(void)
{
	return ARRAY_SIZE(lpddr4_3733_phy_pie);
}

struct DRAM_CFG_PARAM lpddr4_phy_pie_freqs_2666_667[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},

	//p1 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p1, 0x0012},
	#if (LPDDR4_FFS_6335_FSP==0)
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p1, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p1, 0x3},
	#endif

	//p2 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p2, 0x0012},
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p2, 0x5a},//p2 no need
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p2, 0x3},//p2 no need

	//p1
	//P1 = 2666
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p1, 0x53},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p1, 0xa6},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p1, 0x682},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p1, 0x2c},

	//p2
	//P2 = 667
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p2, 0x14},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p2, 0x29},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p2, 0x1a0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p2, 0x10},

	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

struct DRAM_CFG_PARAM lpddr4_phy_pie_freqs_1333_667[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},

	//p1 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p1, 0x0012},
	#if (LPDDR4_FFS_6335_FSP==0)
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p1, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p1, 0x3},
	#endif

	//p2 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p2, 0x0012},
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p2, 0x5a},//p2 no need
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p2, 0x3},//p2 no need

	//p1
	//P1 = 1333
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p1, 0x29},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p1, 0x53},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p1, 0x340},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p1, 0x2c},

	//p2
	//P2 = 667
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p2, 0x14},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p2, 0x29},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p2, 0x1a0},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p2, 0x10},

	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

struct DRAM_CFG_PARAM lpddr4_phy_pie_freqs_1333_333[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},

	//p1 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p1, 0x0012},
	#if (LPDDR4_FFS_6335_FSP==0)
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p1, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p1, 0x3},
	#endif

	//p2 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p2, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p2, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p2, 0x0012},
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p2, 0x5a},//p2 no need
	//{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p2, 0x3},//p2 no need

	//p1
	//P1 = 1333
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p1, 0x176},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p1, 0x53},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p1, 0x340},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p1, 0x2c},

	//p2
	//P2 = 333
	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p2, 0x5d},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p2, 0x14},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p2, 0xcf},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p2, 0x10},

	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

#define lpddr4_phy_pie_freqs_2666_333 lpddr4_phy_pie_freqs_2666_667

struct DRAM_CFG_PARAM lpddr4_phy_pie_freqs_333[] = {
	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x0},
	//p1 same as p0
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x0_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x0_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x1_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x1_p1, 0x0012},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback0x2_p1, 0x00e0},
	{DWC_DDRPHYA_ACSM0__AcsmPlayback1x2_p1, 0x0012},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup_p1, 0x5a},
	{DWC_DDRPHYA_MASTER0__PPTTrainSetup2_p1, 0x3},

	{DWC_DDRPHYA_MASTER0__Seq0BDLY0_p1, 0xa},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY1_p1, 0x14},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY2_p1, 0xcf},
	{DWC_DDRPHYA_MASTER0__Seq0BDLY3_p1, 0x10},

	{DWC_DDRPHYA_APBONLY0__MicroContMuxSel, 0x1},
};

#ifdef SPL_DDR_PKG
void ddr4_pie_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number)
{
	FILE *fp = NULL;
	int pie_size = 0, pie_freq_size = 0, ddr_pie_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return ;
	}

	/* phy_pie */
	pie_size = sizeof(ddr4_phy_pie);
	printf("ddr4 pie size: %d\n", pie_size);
	fwrite(ddr4_phy_pie, 2, pie_size / 2, fp);

	/* pie_freq */
	if (freq == DDR_FREQC_2666) {
		pie_freq_size = sizeof(ddr4_2666_phy_pie);
		fwrite(ddr4_2666_phy_pie, 2, pie_freq_size / 2, fp);
        } else if (freq == DDR_FREQC_2640) {
                pie_freq_size = sizeof(ddr4_2640_phy_pie);
                fwrite(ddr4_2640_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_2400) {
		pie_freq_size = sizeof(ddr4_2400_phy_pie);
		fwrite(ddr4_2400_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_1600) {
		pie_freq_size = sizeof(ddr4_1600_phy_pie);
		fwrite(ddr4_1600_phy_pie, 2, pie_freq_size / 2, fp);
	}

	/* align 512 */
	pie_size = pie_size + pie_freq_size;
	if (pie_size % 512)
		padding_size = 512 - (pie_size % 512);

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}

	hdr_uart.ddr_pie.addr = hdr_uart.ddr_ddrp.addr +
		ALIGN_512(hdr_uart.ddr_ddrp.size);
	hdr_uart.ddr_pie.size = pie_size;

	hdr_ddr.ddr[index].ddr_pie.addr = hdr_ddr.ddr[index].ddr_ddrp_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp_freqs.size);
	hdr_ddr.ddr[index].ddr_pie.size = pie_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_pie_freqs.addr = hdr_ddr.ddr[index].ddr_pie.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_pie.size);
	hdr_ddr.ddr[index].ddr_pie_freqs.size = ddr_pie_dfs_size;

	pclose(fp);
	return;
}

void lpddr4_pie_write_to_bin(char *file, unsigned int freq,
	unsigned int index, unsigned int part_number)
{
	FILE *fp = NULL;
	int pie_size = 0, pie_freq_size = 0, ddr_pie_dfs_size = 0;
	int padding_size = 0, i;
	char padding_value = 0;
	int32_t tmp_dfs_size = 0;

	fp = fopen(file, "ab+");
	if (NULL == fp) {
		printf("File open fail!\n");
		return;
	}

	/* ddrc_cfg */
	pie_size = sizeof(lpddr4_phy_pie);
	fwrite(lpddr4_phy_pie, 2, pie_size / 2, fp);

	/* ddrc_freq */
	if (freq == DDR_FREQC_3733) {
		pie_freq_size = sizeof(lpddr4_3733_phy_pie);
		fwrite(lpddr4_3733_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3600) {
		pie_freq_size = sizeof(lpddr4_3600_phy_pie);
		fwrite(lpddr4_3600_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_3200) {
		if ((part_number == H9HCNNNBKUMLHR)
			|| (part_number == K4F6E3S4HMMGCJ)
			|| (part_number == K4F8E304HBMGCJ)) {
			pie_freq_size = sizeof(lpddr4_3200_phy_pie_dfs);
			fwrite(lpddr4_3200_phy_pie_dfs, 2, pie_freq_size / 2, fp);
		} else {
			pie_freq_size = sizeof(lpddr4_3200_phy_pie);
			fwrite(lpddr4_3200_phy_pie, 2, pie_freq_size / 2, fp);
		}
	} else if (freq == DDR_FREQC_2666) {
		pie_freq_size = sizeof(lpddr4_2666_phy_pie);
		fwrite(lpddr4_2666_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_667) {
		pie_freq_size = sizeof(lpddr4_667_phy_pie);
		fwrite(lpddr4_667_phy_pie, 2, pie_freq_size / 2, fp);
	} else if (freq == DDR_FREQC_100) {
		pie_freq_size = sizeof(lpddr4_100_phy_pie);
		fwrite(lpddr4_100_phy_pie, 2, pie_freq_size / 2, fp);
	}

	/* align 512 */
	pie_size = pie_size + pie_freq_size;
	if (pie_size % 512)
		padding_size = 512 - ((pie_size % 512));

	for (i = 0; i < padding_size; i++) {
		fwrite(&padding_value, 1, 1, fp);
	}
	/*dfs*/
#ifdef YMODEM_BOOT
#else
	if (freq == DDR_FREQC_3200) {
		if (part_number == K4F8E304HBMGCJ) {
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
					DDR_FREQC_2666,
					DDR_FREQC_667,
					lpddr4_phy_pie_freqs_2666_667,
					lpddr4_samsung_1g,
					lpddr4_samsung_1g_cnt);
			if (tmp_dfs_size > 0)
				ddr_pie_dfs_size = tmp_dfs_size;
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
					DDR_FREQC_2666,
					DDR_FREQC_333,
					lpddr4_phy_pie_freqs_2666_333,
					lpddr4_samsung_1g,
					lpddr4_samsung_1g_cnt);
			if (tmp_dfs_size > 0)
				ddr_pie_dfs_size = tmp_dfs_size;

			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
								DDR_FREQC_1333,
								DDR_FREQC_333,
								lpddr4_phy_pie_freqs_1333_333,
								lpddr4_samsung_1g,
								lpddr4_samsung_1g_cnt);
			if (tmp_dfs_size > 0)
				ddr_pie_dfs_size = tmp_dfs_size;
		} else if (part_number == K4F6E3S4HMMGCJ) {
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
				DDR_FREQC_1333,
				DDR_FREQC_333,
				lpddr4_phy_pie_freqs_1333_333,
				lpddr4_samsung_2g,
				lpddr4_samsung_2g_cnt);
			if (tmp_dfs_size > 0)
				ddr_pie_dfs_size = tmp_dfs_size;
		} else if (part_number == H9HCNNNBKUMLHR) {
			tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_3200,
				    DDR_FREQC_333,
				    0,
				    lpddr4_phy_pie_freqs_333,
				    lpddr4_3200_333,
				    lpddr4_3200_333_cnt);
			if (tmp_dfs_size > 0)
				ddr_pie_dfs_size = tmp_dfs_size;
		}
	}
	if (part_number == K4F8E304HBMGCJ && freq == DDR_FREQC_2666) {
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,
						    DDR_FREQC_1333,
						    DDR_FREQC_667,
						    lpddr4_phy_pie_freqs_1333_667,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddr_pie_dfs_size = tmp_dfs_size;
		tmp_dfs_size = LPDDR4_FREQS_CFG_ADD(DDR_FREQC_2666,
						    DDR_FREQC_1333,
						    DDR_FREQC_333,
						    lpddr4_phy_pie_freqs_1333_333,
						    lpddr4_samsung_1g,
						    lpddr4_samsung_1g_cnt);
		if (tmp_dfs_size > 0)
			ddr_pie_dfs_size = tmp_dfs_size;
	}
#endif

	hdr_uart.ddr_pie.addr = hdr_uart.ddr_ddrp.addr +
		ALIGN_512(hdr_uart.ddr_ddrp.size);
	hdr_uart.ddr_pie.size = pie_size;

	hdr_ddr.ddr[index].ddr_pie.addr = hdr_ddr.ddr[index].ddr_ddrp_freqs.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_ddrp_freqs.size);
	hdr_ddr.ddr[index].ddr_pie.size = pie_size;
	/*dfs ddr_ddrc_freqs*/
	hdr_ddr.ddr[index].ddr_pie_freqs.addr = hdr_ddr.ddr[index].ddr_pie.addr +
		ALIGN_512(hdr_ddr.ddr[index].ddr_pie.size);
	hdr_ddr.ddr[index].ddr_pie_freqs.size = ddr_pie_dfs_size;

	pclose(fp);
	return;
}
#endif
